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| 24AA65/24LC65/24C65 64K I2CTM Smart SerialTM EEPROM Device Selection Table Part Number 24AA65 24LC65 24C65 VCC Range 1.8-6.0V 2.5-6.0V 4.5-6.0V Page Size 64 Bytes 64 Bytes 64 Bytes Temp. Ranges C C, I C, I, E Packages P, SM P, SM P, SM Features: * Voltage Operating Range: 1.8V to 6.0V - Peak write current 3 mA at 6.0V - Maximum read current 150 A at 6.0V - Standby current 1 A, typical * Industry Standard Two-Wire Bus Protocol I2CTM Compatible * 8-Byte Page, or Byte modes Available * 2 ms Typical Write Cycle Time, Byte or Page * 64-Byte Input Cache for Fast Write Loads * Up to 8 devices may be connected to the same bus for up to 512K bits total memory * Including 100 kHz (1.8V Vcc < 4.5V) and 400 kHz (4.5V VCC 6.0V) Compatibility * Programmable Block Security Options * Programmable Endurance Options * Schmitt Trigger, Filtered Inputs for Noise Suppression * Output Slope Control to Eliminate Ground Bounce * Self-Timed Erase and Write Cycles * Power-on/off Data Protection Circuitry * Endurance: - 10,000,000 E/W cycles for a High Endurance Block - 1,000,000 E/W cycles for a Standard Endurance Block * Electrostatic Discharge Protection > 4000V * Data Retention > 200 years * 8-pin PDIP/SOIJ Packages * Temperature Ranges - Industrial (I) -40C to +85C - Automotive (E) -40C to +125C * Pb-Free and RoHS Compliant Description: The Microchip Technology Inc. 24AA65/24LC65/ 24C65 (24XX65)* is a "smart" 8K x 8 Serial Electrically Erasable PROM. This device has been developed for advanced, low-power applications such as personal communications, and provides the systems designer with flexibility through the use of many new user-programmable features. The 24XX65 offers a relocatable 4K bit block of ultra-high-endurance memory for data that changes frequently. The remainder of the array, or 60K bits, is rated at 1,000,000 erase/write (E/W) cycles ensured. The 24XX65 features an input cache for fast write loads with a capacity of eight pages, or 64 bytes. This device also features programmable security options for E/W protection of critical data and/or code of up to fifteen 4K blocks. Functional address lines allow the connection of up to eight 24XX65's on the same bus for up to 512K bits contiguous EEPROM memory. Advanced CMOS technology makes this device ideal for low-power nonvolatile code and data applications. The 24XX65 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIJ package. Package Types PDIP A0 A1 A2 VSS 1 8 VCC NC SCL SDA 3 4 24XX65 2 7 6 5 SOIJ A0 A1 A2 1 8 VCC NC SCL SDA 2 3 4 7 6 5 *24XX65 is used in this document as a generic part number for the 24AA65/24LC65/24C65 devices. VSS (c) 2008 Microchip Technology Inc. 24XX65 DS21073K-page 1 24AA65/24LC65/24C65 Block Diagram A0 A1 A2 HV Generator Pin Function Table Name A0, A1, A2 VSS SDA SCL VCC NC Function User Configurable Chip Selects Ground Serial Address/Data/I/O Serial Clock +1.8V to 6.0V Power Supply No Internal Connection I/O Control Logic Memory Control Logic XDEC EEPROM Array Page Latches I/O SCL Cache SDA VCC VSS YDEC Sense Amp. R/W Control DS21073K-page 2 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied................................................................................................-40C to +125C ESD protection on all pins ...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS VCC = +1.8V to +6.0V Commercial (C): TA = Industrial (I): TA = Automotive (E): TA = Sym VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS Min .7 VCC -- .05 VCC -- -- -- -- -- -- -- 0C to +70C -40C to +85C -40C to +125C Max -- .3 VCC -- .40 1 1 10 3 150 5 Units V V V V A A pF mA A A Conditions DC CHARACTERISTICS Parameter A0, A1, A2, SCL and SDA pins: High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Note 1: (Note 1) IOL = 3.0 mA VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note 1) TA = 25C, FCLK = 1 MHz VCC = 6.0V, SCL = 400 kHz VCC = 6.0V, SCL = 400 kHz VCC = 5.0V, SCL = SDA = VCC A0, A1, A2 = VSS This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING START/STOP VHYS SCL TSU:STA SDA THD:STA TSU:STO Start Stop (c) 2008 Microchip Technology Inc. DS21073K-page 3 24AA65/24LC65/24C65 TABLE 1-2: AC CHARACTERISTICS VCC = 1.8V-6.0V STD. Mode Symbol Min Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition setup time Start condition setup time Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- VCC = 4.5-6.0V FAST Mode Min -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns Units Remarks Parameter (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated Start condition Output fall time from VIH min to TOF -- 250 20 + 0.1 250 ns VIL max CB 50 -- 50 -- ns (Note 3) Input filter spike suppression TSP (SDA and SCL pins) -- 5 -- 5 ms/page (Note 4) Write cycle time TWR Endurance High Endurance Block 10M -- 10M -- cycles 25C, (Note 5) Rest of Array 1M -- 1M -- Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write cache for total time. 5: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be downloaded at www.microchip.com. (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF FIGURE 1-2: BUS TIMING DATA TF THIGH TLOW TR SCL TSU:STA THD:STA SDA IN TSP TAA SDA OUT TAA THD:DAT TSU:DAT TSU:STO TBUF DS21073K-page 4 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 2.0 FUNCTIONAL DESCRIPTION 3.3 Stop Data Transfer (C) The 24XX65 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX65 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 3.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24XX65 does not generate any Acknowledge bits if an internal programming cycle is in progress. 3.1 Bus not Busy (A) Both data and clock lines remain high. 3.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX65) must leave the data line high to enable the master to generate the Stop condition. FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS SCL (A) (B) (D) (D) (C) (A) SDA Start Condition Address or Acknowledge Valid Data Allowed To Change Stop Condition (c) 2008 Microchip Technology Inc. DS21073K-page 5 24AA65/24LC65/24C65 3.6 Device Addressing 4.0 4.1 WRITE OPERATION Byte Write A control byte is the first byte received following the Start condition from the master device. The control byte consists of a four-bit control code, for the 24XX65 this is set as `1010' binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the eight devices are to be accessed. These bits are in effect the three Most Significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 4-1). Because only A12..A0 are used, the upper three address bits must be zeros. The Most Significant bit of the Most Significant Byte is transferred first. Following the Start condition, the 24XX65 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a `1010' code and appropriate device select bits, the slave device (24XX65) outputs an Acknowledge signal on the SDA line. Depending upon the state of the R/W bit, the 24XX65 will select a read or write operation. Operation Control Code Read Write 1010 1010 Device Select Device Address Device Address R/W 1 0 Following the Start condition from the master, the control code (four bits), the device select (three bits), and the R/W bit which is a logic low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver (24XX65) that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the Address Pointer of the 24XX65. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24XX65, the master device will transmit the data word to be written into the addressed memory location. The 24XX65 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24XX65 will not generate Acknowledge signals (Figure 4-1). 4.2 Page Write FIGURE 3-2: START CONTROL BYTE ALLOCATION READ/WRITE SLAVE ADDRESS R/W A 1 0 1 0 A2 A1 A0 The write control byte, word address and the first data byte are transmitted to the 24XX65 in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to eight pages of eight data bytes each (64 bytes total), which are temporarily stored in the on-chip page cache of the 24XX65. They will be written from the cache into the EEPROM array after the master has transmitted a Stop condition. After the receipt of each word, the six lower order Address Pointer bits are internally incremented by one. The higher order seven bits of the word address remain constant. If the master should transmit more than eight bytes prior to generating the Stop condition (writing across a page boundary), the address counter (lower three bits) will roll over and the pointer will be incremented to point to the next line in the cache. This can continue to occur up to eight times or until the cache is full, at which time a Stop condition should be generated by the master. If a Stop condition is not received, the cache pointer will roll over to the first line (byte 0) of the cache, and any further data received will overwrite previously captured data. The Stop condition can be sent at any time during the transfer. As with the byte write operation, once the Stop condition is received an internal write cycle will begin. The 64-byte cache will continue to capture data until a Stop condition occurs or the operation is aborted (Figure 4-2). DS21073K-page 6 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 FIGURE 4-1: BYTE WRITE S T A R T S A C K Control Byte Word Address (1) 000 Bus Activity Master SDA Line Bus Activity Word Address (0) Data S T O P P A C K A C K A C K FIGURE 4-2: S T A R T PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 8-2) Bus Activity Master Control Byte Word Address (1) Word Address (0) Data n Data n + 7 S T O P P SDA Line S Bus Activity: A C K 000 A C K A C K A C K A C K FIGURE 4-3: CURRENT ADDRESS READ Bus Activity Master S T A R T S A C K N O A C K Control Byte Data n S T O P P SDA Line Bus Activity (c) 2008 Microchip Technology Inc. DS21073K-page 7 24AA65/24LC65/24C65 FIGURE 4-4: S T A R T SDA Line S RANDOM READ Control Byte Word Address (1) 000 Word Address (0) S T A R T S Control Byte Data n S T O P P Bus Activity A C K A C K A C K A C K N O A C K FIGURE 4-5: Bus Activity Master SDA Line Bus Activity SEQUENTIAL READ Control Byte S T O P P A C K A C K A C K A C K N O A C K Data n Data n + 1 Data n + 2 Data n + X DS21073K-page 8 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 5.0 READ OPERATION 5.4 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read and sequential read. Contiguous Addressing Across Multiple Devices 5.1 Current Address Read The device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 512K bits by adding up to eight 24XX65's on the same bus. In this case, software can use A0 of the control byte as address bit A13, A1 as address bit A14 and A2 as address bit A15. The 24XX65 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24XX65 issues an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24XX65 discontinues transmission (Figure 4-3). 5.5 Noise Protection The SCL and SDA inputs have filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. All I/O lines incorporate Schmitt Triggers for 400 kHz (Fast mode) compatibility. 5.6 High Endurance Block 5.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24XX65 as part of a write operation (R/W bit set to `0'). After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then the master issues the control byte again, but with the R/W bit set to a one. The 24XX65 will then issue an acknowledge and transmit the eight-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition which causes the 24XX65 to discontinue transmission (Figure 4-4). The location of the high endurance block within the memory map is programmed by setting the leading bit 7 (S/HE) of the configuration byte to `0'. The upper bits of the address loaded in this command will determine which 4K block within the memory map will be set to high endurance. This block will be capable of 10,000,000 erase/write cycles typical (Figure 8-1). The high endurance block will retain its value as the high endurance block even if it resides within the security block range. The high endurance setting always takes precedence to the security setting. Note: The high endurance block cannot be changed after the security option has been set with a length greater than zero. If the H.E. block is not programmed by the user, the default location is the highest block of memory which starts at location 0x1E00 and ends at 0x1FFF. 5.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24XX65 transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random read. This acknowledge directs the 24XX65 to transmit the next sequentially addressed 8-bit word (Figure 4-5). Following the final byte transmitted to the master, the master will NOT generate an acknowledge, but will generate a Stop condition. To provide sequential reads the 24XX65 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. (c) 2008 Microchip Technology Inc. DS21073K-page 9 24AA65/24LC65/24C65 5.7 Security Options The 24XX65 has a sophisticated mechanism for write protecting portions of the array. This write-protect function is programmable and allows the user to protect 0-15 contiguous 4K blocks. The user sets the security option by sending to the device the starting block number for the protected region and the number of blocks to be protected. All parts will come from the factory in the default configuration with the starting block number set to 15 and the number of protected blocks set to zero. THE SECURITY OPTION CAN BE SET ONLY ONCE WITH A LENGTH GREATER THAN ZERO. To invoke the security option, a Write command is sent to the device with the leading bit (bit 7) of the first address byte set to a `1' (Figure 8-1). Bits 1-4 of the first address byte define the starting block number for the protected region. For example, if the starting block number is to be set to 5, the first address byte would be 1XX0101X. Bits 0, 5 and 6 of the first address byte are disregarded by the device and can be either high or low. The device will acknowledge after the first address byte. A byte of "don't care" bits is then sent by the master, with the device acknowledging afterwards. The third byte sent to the device has bit 7 (S/HE) set high and bit 6 (R) set low. Bits 4 and 5 are "don't cares" and bits 0-3 define the number of blocks to be write-protected. For example, if three blocks are to be protected, the third byte would be 10XX0011. After the third byte is sent to the device, it will acknowledge and a Stop bit is then sent by the master to complete the command. If one of the security blocks coincides with the high endurance block, the high endurance setting will take precedence. Also, if the range of the security blocks encompass the high endurance block when the security option is set, the security block range will be set accordingly, but the high endurance block will continue to retain the high endurance setting. As a result, the memory blocks preceding the high endurance block will be set as secure sections. During a normal write sequence, if an attempt is made to write to a protected address, no data will be written and the device will not report an error or abort the command. If a Write command is attempted across a secure boundary, unprotected addresses will be written and protected addresses will not. acknowledge the second, and then send a Stop bit to end the sequence. The upper four bits of both of these bytes will always be read as `1's. The lower four bits of the first byte contains the starting secure block. The lower four bits of the second byte contains the number of secure blocks. The default starting secure block is fifteen and the default number of secure blocks is zero (Figure 8-1). 6.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 6-1 for flow diagram. FIGURE 6-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 5.8 Security Configuration Read Did Device Acknowledge (ACK = 0)? YES Next Operation NO The status of the secure portion of memory can be read by using the same technique as programming this option except the read bit (bit 6) of the configuration byte is set to a one. After the configuration byte is sent, the device will acknowledge and then send two bytes of data to the master just as in a normal read sequence. The master must acknowledge the first byte and not DS21073K-page 10 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 7.0 PAGE CACHE AND ARRAY MAPPING fully loaded cache of 64 bytes. Since the cache started loading at byte 2, the last two bytes loaded into the cache will `roll over' and be loaded into the first two bytes of page 0 (of the cache). When the Stop bit is sent, page 0 of the cache is written to page 3 of the array. The remaining pages in the cache are then loaded sequentially to the array. A write cycle is executed after each page is written. If a partially loaded page in the cache remains when the Stop bit is sent, only the bytes that have been loaded will be written to the array. The cache is a 64-byte (8 pages x 8 bytes) FIFO buffer. The cache allows the loading of up to 64 bytes of data before the write cycle is actually begun, effectively providing a 64-byte burst write at the maximum bus rate. Whenever a Write command is initiated, the cache starts loading and will continue to load until a Stop bit is received to start the internal write cycle. The total length of the write cycle will depend on how many pages are loaded into the cache before the Stop bit is given. Maximum cycle time for each page is 5 ms. Even if a page is only partially loaded, it will still require the same cycle time as a full page. If more than 64 bytes of data are loaded before the Stop bit is given, the Address Pointer will `wrap around' to the beginning of cache page 0 and existing bytes in the cache will be overwritten. The device will not respond to any commands while the write cycle is in progress. 7.3 Power Management 7.1 Cache Write Starting at a Page Boundary If a Write command begins at a page boundary (address bits A2, A1 and A0 are zero), then all data loaded into the cache will be written to the array in sequential addresses. This includes writing across a 4K block boundary. In the example shown below, (Figure 8-2) a Write command is initiated starting at byte 0 of page 3 with a fully loaded cache (64 bytes). The first byte in the cache is written to byte 0 of page 3 (of the array), with the remaining pages in the cache written to sequential pages in the array. A write cycle is executed after each page is written. Since the write begins at page 3 and 8 pages are loaded into the cache, the last 3 pages of the cache are written to the next row in the array. The design incorporates a power Standby mode when not in use and automatically powers off after the normal termination of any operation when a Stop bit is received and all internal functions are complete. This includes any error conditions (i.e., not receiving an Acknowledge or Stop condition per the two-wire bus specification). The device also incorporates VDD monitor circuitry to prevent inadvertent writes (data corruption) during low voltage conditions. The VDD monitor circuitry is powered off when the device is in Standby mode in order to further reduce power consumption. 8.0 8.1 PIN DESCRIPTIONS A0, A1, A2 Chip Address Inputs The A0..A2 inputs are used by the 24XX65 for multiple device operation and conform to the two-wire bus standard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte (Figure 3-2 and Figure 8-1). 7.2 Cache Write Starting at a Non-Page Boundary 8.2 SDA Serial Address/Data Input/ Output When a Write command is initiated that does not begin at a page boundary (i.e., address bits A2, A1 and A0 are not all zero), it is important to note how the data is loaded into the cache, and how the data in the cache is written to the array. When a Write command begins, the first byte loaded into the cache is always loaded into page 0. The byte within page 0 of the cache where the load begins is determined by the three Least Significant Address bits (A2, A1, A0) that were sent as part of the Write command. If the Write command does not start at byte 0 of a page and the cache is fully loaded, then the last byte(s) loaded into the cache will roll around to page 0 of the cache and fill the remaining empty bytes. If more than 64 bytes of data are loaded into the cache, data already loaded will be overwritten. In the example shown in Figure 8-3, a Write command has been initiated starting at byte 2 of page 3 in the array with a This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 K for 100 kHz, 2 K for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 8.3 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. (c) 2008 Microchip Technology Inc. DS21073K-page 11 24AA65/24LC65/24C65 FIGURE 8-1: Control Byte 1 0 1 0 A A A R/W 210 CONTROL SEQUENCE BIT ASSIGNMENTS Address Byte 1 S00AAAAA 12 11 10 9 8 Address Byte 0 A A 7******0 Configuration Byte RXXBBBB 3210 Slave Device Address Select Bits S/HE Block Count Security Read S t a r t Acknowledges from Device R Acknowledge from Master Data from Device No ACK S t Data from Device o p A A A A A 1 0 1 0AAA 0C1XXXXXXXCXXXX XXXXC 1 1XXXXXXC1 1 1 1BBBB C 1 111NNNN 210 3210 3210K K K K K S/HE Starting Block Number Number of Blocks to Protect Security Write S t a r t Acknowledges from Device R A A A A 1 0 1 0AAA 0C 1 XXBBBBX CXXXX XXXXC 1 0XXNNNNC 3210K 210 3210 K K K S t o p S/HE Starting Block Number Number of Blocks to Protect High Endurance Block Read S t a r t Acknowledges from Device R No ACK Data from Device S t o p A A A A 1 01 0AAA 0C1XXXXXXXCXXXXXXXXC 0 1XXXXXXC1 1 1 1BBBB 210 3210 K K K K S/HE High Endurance Block Number High Endurance Block Write S t a r t Acknowledges from Device R A A A A 1 01 0AAA 0C1XXBBBBXCXXXXXXXXC 0 0XX0 00 0 C 210 3210 K K K K S t o p High Endurance Block Number S/HE DS21073K-page 12 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 FIGURE 8-2: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY 1 Write command initiated at byte 0 of page 3 in the array; First data byte is loaded into the cache byte 0. cache page 0 cache byte 0 cache byte 1 *** cache byte 7 cache page 1 cache page 2 bytes 8-15 bytes 16-23 *** cache page 7 bytes 56-63 2 64 bytes of data are loaded into cache. 3 Write from cache into array initiated by STOP bit. Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. page 0 page 1 page 2 page 0 page 1 page 2 byte 0 byte 1 *** 4 Remaining pages in cache are written to sequential pages in array. byte 7 page 4 page 4 *** *** page 7 array row n page 7 array row n + 1 page 3 5 Last page in cache written to page 2 in next row. FIGURE 8-3: CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY 1 Write command initiated; 64 bytes of data loaded into cache starting at byte 2 of page 0. cache byte 1 cache byte 2 cache byte 7 2 Last 2 bytes loaded 'roll over' to beginning. cache page 7 bytes 56-63 Last 2 bytes loaded into page 0 of cache. 3 cache byte 0 *** cache page 1 cache page 2 bytes 8-15 bytes 16-23 *** 4 Write from cache into array initiated by STOP bit. 5 Remaining bytes in cache are Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. written sequentially to array. page 7 array row n page 7 array row n+1 page 0 page 1 page 2 page 0 page 1 page 2 byte 0 byte 1 byte 2 byte 3 page 3 byte 4 *** byte 7 page 4 page 4 *** *** 6 Last 3 pages in cache written to next row in array. (c) 2008 Microchip Technology Inc. DS21073K-page 13 24AA65/24LC65/24C65 9.0 9.1 PACKAGING INFORMATION Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW Example: 24LC65 I/P017 0310 8-Lead SOIJ (5.28 mm) XXXXXXXX T/XXXXXX YYWWNNN Example: 24LC65 I/SM 0110017 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS21073K-page 14 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 /HDG 3ODVWLF 'XDO ,Q /LQH 3 1RWH PLO %RG\ >3',3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 D 3 E A A2 A1 L c e b1 b 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 2YHUDOO 5RZ 6SDFLQJ 1 H $ $ $ ( ( ' / F E E H% %6& 0,1 ,1&+(6 120 0$; eB 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWK WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % (c) 2008 Microchip Technology Inc. DS21073K-page 15 24AA65/24LC65/24C65 /HDG 3ODVWLF 6PDOO 2XWOLQH 60 0HGLXP 1RWH PP %RG\ >62,-@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 1 b 2 e c A A2 A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK )RRW /HQJWK )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' / I F E D E 0,1 0,//,0(7(56 120 %6& L 0$; 1RWHV 62,- -(,7$ (,$- 6WDQGDUG IRUPHUO\ FDOOHG 62,& 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH % 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & DS21073K-page 16 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2008 Microchip Technology Inc. DS21073K-page 17 24AA65/24LC65/24C65 APPENDIX A: Revision J Corrections to Section 1.0, Electrical Characteristics. REVISION HISTORY Revision K (07/2008) Revised Temperature ranges; Ambient temperature; Revised Package Drawings; Replaced On-line Support; Revised Product ID System. DS21073K-page 18 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2008 Microchip Technology Inc. DS21073K-page 19 24AA65/24LC65/24C65 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS21073K FAX: (______) _________ - _________ Device: 24AA65/24LC65/24C65 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21073K-page 20 (c) 2008 Microchip Technology Inc. 24AA65/24LC65/24C65 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) 24LC65T-I/SM: 64 Kbit Smart Serial, Tape and Reel, 5.28 mm SOIJ package, Industrial temperature, 2.5V 24LC65-I/P: 64 Kbit Smart Serial, Industrial temperature, PDIP package, 2.5V 24AA65T-/SM: 64 Kbit Smart Serial, Tape and Reel, 5.28 mm SOIJ package, Commercial temperature, 1.8V 24C65-E/P: 64 Kbit Smart Serial, Automotive temperature, PDIP, 5V Device: 24AA65 - 64K I2C 1.8V Serial EEPROM (100 kHz) 24AA65T - 64K I2C 1.8V Serial EEPROM (100 kHz) 24LC65 - 64K I2C Serial EEPROM (100 kHz/400 kHz) 24LC65T - 64K I2C Serial EEPROM (Tape and Reel) 24C65 - 64K I2C 4.5V Serial EEPROM (400 kHz) 24C65T - 64K I2C 4.5V Serial EEPROM (Tape and Reel) b) c) d) Temperature Range: I E = -40C to +85C = -40C to +125C Package: P SM = = Plastic DIP (300 mil Body) Plastic SOIJ (5.28 mm Body, EIAJ standard) (c) 2008 Microchip Technology Inc. DS21073K-page 21 24AA65/24LC65/24C65 NOTES: DS21073K-page 22 (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. DS21073K-page 23 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/02/08 DS21073K-page 24 (c) 2008 Microchip Technology Inc. |
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